bitwise operations
This commit is contained in:
+122
-1
@@ -260,7 +260,8 @@ valid_value :: proc(
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.Neg_Checked, .Add_Checked, .Sub_Checked, .Mul_Checked, .Div_Checked,
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.Div_Trunc_Checked, .Div_Floor_Checked, .Div_Exact_Checked, .Div_Ceil_Checked,
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.Rem_Checked, .Mod_Checked,
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.Pointer_Add, .Not, .Compare, .Call:
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.Pointer_Add, .Not, .Bit_Not, .Bit_And, .Bit_Or, .Bit_Xor,
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.Shift_Left, .Shift_Right, .Shift_Left_Saturating, .Compare, .Call:
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return true
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case .Address_Global, .Alloca, .Index_Address, .Field_Address, .Orelse_Begin,
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.Store, .Fill, .Trap, .Label, .Br, .Cond_Br, .Return, .Return_Void:
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@@ -814,6 +815,94 @@ emit_division_builtin :: proc(
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}
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}
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emit_shift :: proc(
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emitter: ^Emitter,
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instructions: []ir.Instruction,
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instruction_index: int,
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instruction: ir.Instruction,
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) {
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count_type := types.INVALID
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if valid_instruction(instructions, instruction.b) {
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count_type = instructions[instruction.b].type
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}
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if !types.is_concrete_integer(instruction.type) ||
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!valid_value(instructions, instruction.a, instruction.type, &emitter.module.types) ||
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!types.is_concrete_integer(count_type) || !types.is_unsigned(count_type, emitter.module.target) ||
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!valid_value(instructions, instruction.b, count_type, &emitter.module.types) {
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emit_recovery_value(emitter, instruction_index, instruction, "invalid shift operands")
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return
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}
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type_name := llvm_type(instruction.type, &emitter.module.types)
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bits := types.bits(instruction.type, emitter.module.target)
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count_bits := types.bits(count_type, emitter.module.target)
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if count_bits < 64 {
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fmt.sbprintf(&emitter.builder, " %%shift_count64_%d = zext %s ", instruction_index, llvm_type(count_type, &emitter.module.types))
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write_operand(&emitter.builder, instructions, instruction.b, count_type, &emitter.module.types)
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strings.write_string(&emitter.builder, " to i64\n")
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} else {
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fmt.sbprintf(&emitter.builder, " %%shift_count64_%d = select i1 true, i64 ", instruction_index)
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write_operand(&emitter.builder, instructions, instruction.b, count_type, &emitter.module.types)
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strings.write_string(&emitter.builder, ", i64 0\n")
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}
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fmt.sbprintf(&emitter.builder, " %%shift_in_range%d = icmp ult i64 %%shift_count64_%d, %d\n", instruction_index, instruction_index, bits)
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if instruction.op != .Shift_Left_Saturating {
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fmt.sbprintf(
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&emitter.builder,
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" br i1 %%shift_in_range%d, label %%shift_continue%d, label %%shift_trap%d\nshift_trap%d:\n",
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instruction_index, instruction_index, instruction_index, instruction_index,
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)
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message := diagnostic_message(emitter, source.INVALID_DIAGNOSTIC, instruction.span, "shift count exceeds integer width")
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emit_trap_call(emitter, message)
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fmt.sbprintf(&emitter.builder, " unreachable\nshift_continue%d:\n", instruction_index)
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if bits < 64 {
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fmt.sbprintf(&emitter.builder, " %%shift_count%d = trunc i64 %%shift_count64_%d to %s\n", instruction_index, instruction_index, type_name)
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}
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operation := "shl"
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if instruction.op == .Shift_Right {
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operation = "ashr" if types.is_signed(instruction.type, emitter.module.target) else "lshr"
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}
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fmt.sbprintf(&emitter.builder, " %%v%d = %s %s ", instruction_index, operation, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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if bits < 64 {
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fmt.sbprintf(&emitter.builder, ", %%shift_count%d\n", instruction_index)
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} else {
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fmt.sbprintf(&emitter.builder, ", %%shift_count64_%d\n", instruction_index)
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}
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return
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}
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// LLVM's saturating shift intrinsics produce poison for oversized counts.
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// Select zero before narrowing, then explicitly select the Zig endpoint.
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fmt.sbprintf(&emitter.builder, " %%shift_safe64_%d = select i1 %%shift_in_range%d, i64 %%shift_count64_%d, i64 0\n", instruction_index, instruction_index, instruction_index)
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if bits < 64 {
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fmt.sbprintf(&emitter.builder, " %%shift_safe%d = trunc i64 %%shift_safe64_%d to %s\n", instruction_index, instruction_index, type_name)
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}
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signed := types.is_signed(instruction.type, emitter.module.target)
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intrinsic := "sshl" if signed else "ushl"
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fmt.sbprintf(&emitter.builder, " %%shift_saturated%d = call %s @llvm.%s.sat.%s(%s ", instruction_index, type_name, intrinsic, type_name, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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if bits < 64 {
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fmt.sbprintf(&emitter.builder, ", %s %%shift_safe%d)\n", type_name, instruction_index)
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} else {
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fmt.sbprintf(&emitter.builder, ", i64 %%shift_safe64_%d)\n", instruction_index)
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}
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fmt.sbprintf(&emitter.builder, " %%shift_nonzero%d = icmp ne %s ", instruction_index, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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strings.write_string(&emitter.builder, ", 0\n")
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if signed {
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minimum := -(i128(1) << u32(bits-1))
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maximum := (i128(1) << u32(bits-1))-1
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fmt.sbprintf(&emitter.builder, " %%shift_negative%d = icmp slt %s ", instruction_index, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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fmt.sbprintf(&emitter.builder, ", 0\n %%shift_nonzero_endpoint%d = select i1 %%shift_negative%d, %s %d, %s %d\n", instruction_index, instruction_index, type_name, minimum, type_name, maximum)
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fmt.sbprintf(&emitter.builder, " %%shift_endpoint%d = select i1 %%shift_nonzero%d, %s %%shift_nonzero_endpoint%d, %s 0\n", instruction_index, instruction_index, type_name, instruction_index, type_name)
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} else {
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fmt.sbprintf(&emitter.builder, " %%shift_endpoint%d = select i1 %%shift_nonzero%d, %s -1, %s 0\n", instruction_index, instruction_index, type_name, type_name)
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}
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fmt.sbprintf(&emitter.builder, " %%v%d = select i1 %%shift_in_range%d, %s %%shift_saturated%d, %s %%shift_endpoint%d\n", instruction_index, instruction_index, type_name, instruction_index, type_name, instruction_index)
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}
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emit_instruction_stream :: proc(
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emitter: ^Emitter,
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instructions: []ir.Instruction,
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@@ -1818,6 +1907,36 @@ emit_instruction_stream :: proc(
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fmt.sbprintf(&emitter.builder, " %%v%d = getelementptr %s, ptr %%v%d, i64 ", instruction_index, llvm_type(result_item.child, &emitter.module.types), instruction.a)
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write_operand(&emitter.builder, instructions, instruction.b, types.USIZE, &emitter.module.types)
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strings.write_string(&emitter.builder, "\n")
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case .Bit_Not:
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if !types.is_concrete_integer(instruction.type) ||
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!valid_value(instructions, instruction.a, instruction.type, &emitter.module.types) {
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emit_recovery_value(emitter, instruction_index, instruction, "invalid bitwise complement operand")
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continue
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}
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type_name := llvm_type(instruction.type, &emitter.module.types)
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fmt.sbprintf(&emitter.builder, " %%v%d = xor %s ", instruction_index, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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strings.write_string(&emitter.builder, ", -1\n")
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case .Bit_And, .Bit_Or, .Bit_Xor:
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if !types.is_concrete_integer(instruction.type) ||
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!valid_value(instructions, instruction.a, instruction.type, &emitter.module.types) ||
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!valid_value(instructions, instruction.b, instruction.type, &emitter.module.types) {
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emit_recovery_value(emitter, instruction_index, instruction, "invalid bitwise operands")
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continue
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}
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operation := "and"
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#partial switch instruction.op {
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case .Bit_Or: operation = "or"
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case .Bit_Xor: operation = "xor"
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}
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type_name := llvm_type(instruction.type, &emitter.module.types)
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fmt.sbprintf(&emitter.builder, " %%v%d = %s %s ", instruction_index, operation, type_name)
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write_operand(&emitter.builder, instructions, instruction.a, instruction.type, &emitter.module.types)
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strings.write_string(&emitter.builder, ", ")
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write_operand(&emitter.builder, instructions, instruction.b, instruction.type, &emitter.module.types)
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strings.write_string(&emitter.builder, "\n")
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case .Shift_Left, .Shift_Right, .Shift_Left_Saturating:
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emit_shift(emitter, instructions, instruction_index, instruction)
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case .Call:
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function_id := ir.as_function(instruction.target)
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if function_id == ir.INVALID_FUNCTION {
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@@ -2488,6 +2607,8 @@ emit_declarations :: proc(emitter: ^Emitter) {
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strings.write_string(&emitter.builder, ".with.overflow.i")
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fmt.sbprintf(&emitter.builder, "%d(i%d, i%d)\n", bits, bits, bits)
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}
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fmt.sbprintf(&emitter.builder, "declare i%d @llvm.sshl.sat.i%d(i%d, i%d)\n", bits, bits, bits, bits)
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fmt.sbprintf(&emitter.builder, "declare i%d @llvm.ushl.sat.i%d(i%d, i%d)\n", bits, bits, bits, bits)
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}
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strings.write_string(
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&emitter.builder,
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